As known, conventional NAND flash memory devices typically multiplex input/output (I/O) lines for receiving command, address, and data signals. Some commands, such as a program (i.e., write) command, require all three different types of information to be provided to the memory device. That is, in order to program memory cells with new data, a write command is issued, then the address of the memory cells that will be programmed is provided, and finally, data to be programmed is provided. A confirmation command is typically issued after the data is provided to the memory device indicating the end of the command. All of this information is provided to the memory device using the same I/O lines.
Control signals are used to differentiate the types of signals when latching the different information into the memory device. For example, typical control signals CLE and ALE are brought to a HIGH logic level to indicate to the memory device that the signals that will be latched in response to the next rising edge of a write enable signal (WE#) are either a command or an address, respectively. Thus, when the CLE signal is HIGH (and the ALE signal is LOW), the signals latched from the I/O lines in response to a rising edge of the WE# signal represent a command. In contrast, when the ALE signal is HIGH (and the CLE signal is LOW), the signals latched from the I/O lines in response to a rising edge of the WE# signal represent an address. When both the CLE and ALE signals are LOW, the signals latched from the I/O lines in response to a rising edge of the WE# signal represent data.
FIG. 1 illustrates a conventional input signal path 100 for receiving and internally routing commands and addresses that are latched by a data latch 108 from signals applied to a DQ pad and buffer 104. The DQ pad and buffer 104 represents the I/O signal lines to which external command, address, and data signals are applied to the memory. The signals are latched by the data latch 108 in response to the WE# signal, and commands and addresses are provided to a command decoder 112 and column address latches 122-127, respectively, which are all coupled to an output of the data latch 108. Conventional clock logic 118 generates various internal clock signals and pulses in response to the CLE, ALE and WE# signals to clock the address latches 122-127 and clock a command state machine 116 to generate internal control signals for executing the command in response to receiving the internal command signals from the command decoder 112. Gating logic 120, 130, 140, 150, 160 are used to couple Clk_add—1st-Clk_add—5th signals to respective address latches 122-127 when an active enable signal is output by the command state machine 116. The enable signal is active for commands that require latching of addresses, for example, read and program commands.
As will be explained in more detail below, the input signal path 100 is shown to receive an address having five parts over five WE# clock cycles, each part including up to 8 bits of the total address. As shown, the address latch 122 is clocked by the Clk_add—1st signal to latch bits 0-7 (eight bits) of a first part of the address, the address latch 123 is clocked by the Clk_add—2nd signal to latch bits 0-3 (four bits) of a second part of the address, the address latches 124, 125 are clocked by the Clk_add—3rd signal to latch bits 0-5 (six bits) and bits 6-7 (two bits), respectively, of the third part of the address, the address latch 126 is clocked by the Clk_add—4th signal to latch bits 0-7 (eight bits) of the fourth part of the address, and the address latch 127 is clocked by the Clk_add—5th signal to latch bits 0-1 (two bits) of the fifth part of the address.
FIG. 2 is a timing diagram of various signals of the input signal path 100 during a page read operation. At time T1 the CLE signal transitions HIGH to indicate to the memory that the signals provided to the DQ pad and buffer 104 (represented in FIG. 2 as Padq signals) at the next rising edge of the WE# signal represent a command. The command signals are provided to the DQ pad and buffer 104 shortly after the CLE signal goes HIGH and the WE# signal transitions HIGH at time T2 to clock the data latch 108 to latch the signals at the DQ pad and buffer 104. As shown in FIG. 2, the command provided to the memory is a page read command 00H. After a response and propagation delay of the data latch 108, the latched 00H command is output by the data latch 108 (represented in FIG. 2 as the Dqin signals) to the command decoder 112 at time TA. The command decoder 112 decodes the 00H command and generates internal command signals (not shown) to be provided to the command state machine 116. The command state machine 116 receives the internal command signals and begins generating internal control signals in response to a ltcmd pulse at times TB-TC . The ltcmd signal is generated in response to the previous clock cycle of the WE# signal and the HIGH CLE signal.
During the time the data latch 108 is latching the 00H command, the command decoder 112 is generating the internal command signals, and the command state machine 116 begins generating internal control signals at time TB, the CLE signal provided to the memory is transitioned LOW at time T3 and the ALE signal is transitioned HIGH at time T4 to indicate that the signals provided to the memory on DQ pad and buffer 104 at the next rising edge of the WE# signal represent addresses. As shown in FIG. 2, the address provided to the memory is the first address A1 of five parts of addresses (i.e., A1-A5). The rising edge of the WE# signal at time T5 clocks the data latch 108 and shortly thereafter at time TD the latched address is output at time TD. The Clk_add—1st pulse is HIGH at times TE-TF to clock the address latch 122 to latch bits 0-7 of the A1 address.
Before the next rising edge of the WE# signal at time T6 (ALE continues to be HIGH), the signals provided to the DQ pad and buffer 104 are changed to the second address A2 of the five part address. The A2 address is latched by the data latch 108 in response to the rising edge of the WE# signal at time T6. The signals provided to the DQ pad and buffer 104 are latched, and after a response and propagation delay, the A2 address is output by the data latch 108 at time TG. The Clk_add—2nd pulse at times TH-TI clocks the address latch 123 to latch bits 0-3 of the A2 address.
The third through fifth addresses A3-A5 are latched in a similar manner by the rising edges of the WE# signal at times T7-T9, with the rising edge of the WE# signal clocking the data latch 108 to latch the A3 address at time T7 (with the A3 address available at time TJ to be latched by address latches 124, 125 in response to the Clk_add—3rd pulse at times TK-TL), the rising edge of the WE# signal clocking the data latch 108 to latch the A4 address at time T8 (with the A4 address available at time TM to be latched by address latch 126 in response to the Clk_add—4th pulse at times TN-TO), and the rising edge of the WE# signal clocking the data latch 108 to latch the A5 address at time T9 (with the A5 address available at time TP to be latched by address latch 127 in response to the Clk_add—5th pulse at times TQ-TR). At time T10, the ALE signal is transitioned low indicating that no more addresses will be provided to the memory.
At time T11, the CLE signal is transitioned HIGH to indicate that another command will be provided to the memory over the DQ pad and buffer 104. A confirmation command (i.e., 30H) is issued to the memory to indicate the end of the current command. At the next rising edge of the WE# signal at time T12, the 30H command is latched by the data latch 108 and the CLE signal is transitioned LOW at time T13 to end provision of the current command. With the 30H command latched at T12, the output of the data latch 108 provides the 30H command at time TS to the command decoder 112. The command decoder 112 decodes the 30H command and generates internal command signals. In response to the ltcmd pulse at times TT-TU, the command state machine 116 inputs the internal command signals and generates corresponding internal control signals. A status command (70H) is also issued to the memory by transitioning the CLE signal HIGH at time T14 and providing a 70H command prior to the next rising edge of the WE# signal. The data latch 108 is clocked by the rising edge of the WE# signal at time T15 to latch the 70H command. Soon after latching, the output of the data latch 108 provides the 70H command to the command decoder 112 at time TV. Internal command signals are generated and are provided to the command state machine 116, which inputs the internal command signals in response to the ltcmd pulse at times TW-TX.
In programming data to the memory, the time for the program operation to complete can be divided into three different time ranges: (1) command and address writing time, (2) data loading time, and (3) programming time. Using an example of a write cycle time tWC of 35 ns (i.e., the period of the WE# signal), the three time ranges can typically be about 245 ns (i.e., 7×35 ns) for command and address writing time, 150 us for the programming time, and assuming that data for a full page is being loaded (further assuming a page is 2 kbytes and a byte-wide I/O lines), 71.7 us (i.e., 35 ns×2 kbytes) for the data loading time. As illustrated by the present example, the command and address writing time is nearly negligible, but the data loading time can be almost one-third of the total time for the program operation to complete.
In an effort to decrease the overall time for a program operation to complete, which is considered desirable, manufacturers are allows the use of shorter tWC to reduce the data loading time. A small decrease in tWC may have a relatively large impact where considerable data, such as data for an entire page, is being loaded. However, as the allowable tWC is decreased, internal timing margins of the memory may be decreased as well, raising potential issues with proper operation. This can be illustrated with reference to the timing diagram of FIG. 2. Although the timing diagram of FIG. 2 is directed to a page read command, decreasing tWC affects the internal timing margins of both read and program operations.
As previously discussed, the Dqin signal represents the output of the data latch 108, to which the command decoder 112/command state machine 116 and address latches 122-127 are coupled. As known, the command decoder 112/command state machine 116 and the address latches 122-127 need to receive and latch the respective data before the output of the data latch 108 changes in response to latching of signals at the next rising edge of the WE#. As shown in FIG. 2, the output of the data latch 108 generally transitions after a time of tWC. As previously described, pulses of the ltcmd signal are used to clock the command state machine 116 and pulses of the Clk_add—1 st-Clk_add—5th signals are used to clock the address latches 122-127. The pulses of the ltcmd and Clk_add—1st-Clk_add—5th signals are generated in response to the previous rising edge of the WE# signal. For example, pulses 202, 214, and 216 of the ltcmd signal are generated in response to the rising edges of the WE# signal at time T2, T13, and T15, respectively, to latch the commands 00H, 30H, and 70H from Dqin. Pulses 204-212 of the Clk_add—1st-Clk_add—5th signals are generated in response to the rising edges of the WE# signal at times T5-T9, respectively, to latch addresses A1-A5 from Dqin.
For command and addresses to be accurately latched from Dqin, the pulses must occur at a time when the Dqin signals are stable. As known, the timing of pulses (i.e., when the pulses occur) and pulse width can vary slightly due to changes in temperature and supply voltage. To accommodate variations in timing and pulse width, the pulses occur after a minimum internal set-up time after a transition of the Dqin signals. The pulse width should be sufficient to clock a latch circuit to latch the signals, but leave a minimum internal hold time before a next transition of the Dqin signals. With reference to FIG. 2, and for the pulse 202 clocking the command state machine 116, the set-up time is between TA-TB, the pulse width between TB-TC, and the hold time between TC-TD. As for the pulse 204 clocking the address latch 122, the set-up time is between TD-TE, the pulse width between TE-TF, and the hold time between TF-TG. The set-up, pulse width, and hold times for the pulses 204-216 are generally the same as for the pulses 202 and 204.
As a shorter tWC is used (resulting in a shorter period of WE#) to reduce data load time, as previously discussed, the set-up time, hold time, pulse width or all three will also be reduced, thus, reducing the timing margin for accurately latching the command, address, and data signals. As a result, a lower limit to tWC exists due to the variations in the timing and pulse width of the latch pulses. In order for tWC to be further reduced, there is a need for a input signal path that provides timing margin for latching input signals provided to a memory while allowing the use of a shorter tWC.